Encoding/decoding n-bit source words into corresponding m-bit channel words, and vice versa, such that the conversion is parity inverting

ABSTRACT

A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C), wherein the bitstream of the source signal is divided into n-bit source words (x 1 , x 2 ), which device comprises converting means (CM) adapted to convert said source words into corresponding m-bit channel words (y 1 , y 2 , y 3 ). The converting means (CM) are further adapted to convert n-bit source words into corresponding m-bit channel words, such that the conversion for each n-bit source word is parity inverting (table I) (FIG.  1 ). The relations hold that m&gt;n≧1, p≧1, and that p is an odd integer that can vary. Preferably, m=n+1.  
     Further, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.(FIG.  5 ).

[0001] The invention relates to a device for encoding a stream ofdatabits of a binary source signal into a stream of databits of a binarychannel signal, wherein the bitstream of the source signal is dividedinto n-bit source words, which device comprises converting means adaptedto convert said source words into corresponding m-bit channel words andto a method. The invention also relates to a device for decoding astream of data bits of a binary channel signal obtained by means of theencoding device, so as to obtain a stream of databits of a binary sourcesignal.

[0002] An encoding device mentioned in the foregoing is known from thebook ‘Coding techniques for digital recorders’ by K. A. SchouhamerImmink, chapter 5.6.7, pp. 127 to 131, Prentice Hall (1991). The bookdiscusses an encoder for generating a (d,k) sequence which satisfies theparameters: rate ⅔, (1,7), which encoder is also proposed by Cohn et alin U.S. Pat. No. 4,337,458. The known encoding scheme suffers from thepresence of a DC level which may become excessively large and thereforeintroduces distortion in communication systems which can not handle a DCcomponent, as well as distortion in any recording of data in magneticmedia.

[0003] The invention has for its object to provide a device for encodingn-bit source words into corresponding m-bit channel words, such that ititself does not generate a DC component in the channel signal, whereasfurther it provides the possibility, by means of additional measures tobe taken, to realize a channel signal in the form of a (d,k) sequence.

[0004] The device in accordance with the invention is characterized inthat the converting means are adapted to convert a block of pconsecutive n-bit source words into a corresponding block of pconsecutive m-bit channel words, such that the conversion for each blockof p consecutive n-bit source words is parity inverting, where n, m andp are integers, m>n≧1, p≧1, and where p is an odd integer and can vary.‘Parity inverting’ means that the parity of the n-bit source words to beconverted are the inverse of the parity (after modulo-2 addition) of thecorresponding m-bit channel words in which they are converted. As aresult, a unique relationship between the parity of the source words andthe parity of the channel words can be obtained, enabling an efficientDC control for the binary channel signal, after aT precoding.

[0005] The encoding device in accordance with the invention can be usedin combination with a bit-adder unit in which one bit is added tocodewords of a certain length. The signal obtained can be applied to theencoding device of the present invention. The channel signal of theencoding device is applied to a 1 T-precoder. The purpose of thebit-adder unit is to add a ‘0’- or a ‘1’-bit to blocks of data in theinput signal of the converter, so as to obtain a precoder output signalwhich is DC free, or includes a tracking pilot signal having a certainfrequency. The precoder output signal is recorded on a record carrier.The adding of a ‘0’-bit in the input signal of the converter results inthe polarity of the output signal of the 1 T precoder remaining thesame. The adding of a ‘1’-bit results in a polarity inversion in theoutput signal of the 1 T precoder. The converter therefore influencesthe output signal of the 1 T precoder such that the running digital sumvalue of the output. signal of the 1 T precoder can be controlled so asto have a desired pattern as a function of time.

[0006] Because of the fact that the encoding device in accordance withthe invention realizes a parity-inverting encoding, it does notinfluence the polarity of the signal it encodes and can therefore beused in combination with the bit-adder unit without the need of anymodification.

[0007] Preferably, m equals n+1, and n is equal to 2. For n being equalto 1 or 2, the device in accordance with the invention can be used, withadditional measures to be taken, as will become apparent later, forgenerating channel signals in the form of a (d,k) sequence, where d=1.Higher values for n do not allow for the generation of a (l,k) sequence.Further, n=1, which means that 1-bit source words are converted into2-bit channel words, results in an increase of 100% in bits in thechannel signal generated by the device. Contrary to this a conversion of2-bit source words into 3-bit channel words results in an increase ofonly 50%, and is therefore more advantageous.

[0008] Various conversions of 2-bit source words into 3-bit channelwords are possible, that have the parity inverting character. One suchconversions is the subject of claim 4. It should however be noted thatvarious permutations of the channel codes in the table are possible,namely in total 4.

[0009] The device in accordance with the invention wherein theconverting means are adapted to convert 2-bit source words intocorresponding 3-bit channel words, so as to obtain a channel signal inthe form of a (d,k) sequence, where d=1, the device further comprisingmeans for detecting the position in the bitstream of the source signalwhere encoding of single 2-bit source words into corresponding singlechannel words would lead to a violation of the d-constraint at thechannel word boundaries and for supplying a control signal in responseto said detection, may be further characterized in that in the absenceof the control signal, the converting means are adapted to convertsingle 2-bit source words into corresponding single 3-bit channel words,such that the conversion for each 2-bit source word is parity inverting.More specifically, the device is characterized in that, in the presenceof said control signal, the converting means are further adapted toconvert the block of said two subsequent 2-bit source words into acorresponding block of two subsequent 3-bit channel words, such that theconversion for said block of two subsequent 2-bit source words is paritypreserving. The measure to convert one (say: the second one) of twosubsequent source words into a 3-bit word not identical to the fourchannel words CW₁ to CW₄, offers the possibility to detect at thereceiver side that a situation existed that encoding of single sourcewords into corresponding single channel words would have led to aviolation of the d=1 constraint. The encoder now encodes a block of two2-bit source words into a block of 2 3-bit channel words, such that theencoding of the block is parity preserving, whilst the d=1 constraint issatisfied as well.

[0010] To embody the encoding of blocks of two 2-bit source words, thedevice in accordance with the invention may be characterized in that theconverting means are adapted to convert the blocks of two consecutive2-bit source words into the blocks of two consecutive 3-bit channelwords in accordance with the coding given in the following table: blockof 2 source words block of 2 channel words 01 01 100 010 01 00 101 01011 01 000 010 11 00 001 010

[0011] The device in accordance with the invention, for generating a(d,k) sequence, wherein k has a value larger than 5, the device beingfurther provided with means for detecting the position in the bitstreamof the source signal where encoding of single 2-bit source words intosingle 3-bit channel words would lead to a violation of the k-constraintand for supplying a second control signal in response to said detection,may be further characterized in that, in the presence of the secondcontrol signal, occurring during the conversion of three consecutive2-bit source words, the converting means are adapted to convert a blockof said three consecutive 2-bit source words into a block ofcorresponding three consecutive 3-bit channel words, such that theconversion for said block of three 2-bit source words is parityinverting, the converting means are further adapted to convert two ofthe three source words in the block into corresponding 3-bit channelwords not identical to the four channel words CW₁ to CW₄, in order topreserve the k constraint.

[0012] This measure enables an encoding of a block of three 2-bit sourcewords into a block of three 3-bit channel words so as to satisfy thek-constraint,and such that the encoding is still parity inverting.

[0013] The measure to convert two (say: the second and the third one) ofthree subsequent source words into a 3-bit word not identical to thefour channel words CW₁ to CW₄, offers the possibility to detect at thereceiver side that a situation existed that the encoding of single 2-bitsource words into corresponding single 3-bit channel words would haveled to a violation of the k constraint. Upon detection, the decoder iscapable of decoding the block of three 3-bit channel words into thecorresponding block of three 2-bit source words in the inverse way, asupon encoding.

[0014] To embody the encoding of blocks of three 2-bit source words, thedevice in accordance with the invention may be characterized in that theconverting means are adapted to convert blocks of three consecutive2-bit source words into blocks of three consecutive 3-bit channel wordsin accordance with the coding given in the following table: block of 3source words block of 3 channel words 10 10 10 000 010 010 10 10 11 001010 010 00 10 11 101 010 010 00 10 10 100 010 010

[0015] A device for decoding a stream of data bits of a binary channelsignal into a stream of databits of a binary source signal, wherein thebitstream of the channel signal is divided into m-bit channel words,which device comprises deconverting means adapted to deconvert m-bitchannel words into corresponding n-bit source words, is characterized inthat, the deconverting means are adapted to deconvert a block of pconsecutive m-bit channel words into a corresponding block of pconsecutive n-bit source words, such that the conversion for each blockof p consecutive m-bit channel words is parity inverting, where n, m andp are integers, m>n, p≧1, and where p is an odd integer and can vary.

[0016] It should be noted that published European patent application199.088A2 discloses a converter for converting n-bit source words into achannel signal in the form of a sequence of m-bit channel words, whichchannel signal is DC free. The conversion is however not parityinverting.

[0017] The invention will be further described in the following figuredescription, in which

[0018]FIG. 1 shows a first,

[0019]FIG. 2a shows a second,

[0020]FIG. 2b a third, and

[0021]FIG. 3 shows a fourth embodiment of the device,

[0022]FIG. 4 the application of the device in an arrangement forinserting one bit on equidistant positions in the serial source signal,and

[0023]FIG. 5 an embodiment of the decoding device.

[0024]FIG. 1 shows a device having an input terminal 1, for receiving astream of databits of a binary source signal S. The terminal 1 iscoupled to an input of a shift register 2 having two cells X₁ and X₂ soas to receive two consecutive source bits of the source signal S. Theshift register 2 functions as a serial-parallel converter, so as toobtain consecutive 2-bit source words SW. The outputs of the two cellsare coupled to two inputs i₁, i₂ of a logic circuit LC, for supplyingthe logic values (x₁,x₂) of the source bits present in the cells to thelogic circuit LC.

[0025] The device further includes a second shift register 4 havingthree cells Y₁, Y₂ and Y₃. Outputs o₁, o₂ and o₃ of the logic circuit LCare coupled to inputs of the three cells Y₁, Y₂ and Y₃ respectively ofthe shift register 4, for supplying the logic values (y₁,y₂,y₃) of thechannel words. An output 6 of the shift register 4 is coupled to anoutput terminal 8. The shift register 4 functions as a parallel-serialconverter, so as to convert the 3-bit channel words CW supplied by thelogic circuit LC into a serial stream of databits of a binary channelsignal C.

[0026] The logic circuit LC is adapted to convert consecutive 2-bitsource words SW into 3-bit channel words, such that the conversion foreach 2-bit source word is parity inverting.

[0027] That means that the number of ‘ones’ in the source word to beconverted is the ‘inverse’ of the number of ‘ones’ in the correspondingchannel word, if necessary, after having carried out a modulo-2 additionon the ‘ones’ in the channel word. Or, otherwise said: if the number of‘ones’ in the source word is even, the number of ‘ones’ in the channelword will be odd. And: if the number of ‘ones’ in the source word isodd, the number of ‘ones’ in the channel word will be even.

[0028] As an example, the converting means LC is adapted to convert the2-bit source words SW into 3-bit channel words CW in accordance with thefollowing table: TABLE I source word channel word (x₁,x₂) (y₁,y₂,y₃) SW₁01 CW₁ 101 SW₂ 00 CW₂ 100 SW₃ 11 CW₃ 001 SW₄ 10 CW₄ 000

[0029] It should be noted here, that the first bit in the source word isapplied first to the shift register 2 and that the first bit in thechannel word is supplied first from the output 6 of the shift register4.

[0030] The bitstream of the channel words is in NRZI (non-return tozero-inverse) notation, which means that a ‘one’ results in a transitionin the write current for recording the channel signal on a magneticrecord carrier.

[0031] The device of FIG. 1 can be used to generate a channel signal Cin the form of a (d,k) sequence satisfying the d=1 constraint. Thatmeans that at least one ‘zero’ is present between two subsequent ‘ones’in the serial datastream of the channel signal. That is, that aconcatenation of two or more ‘ones’ in the channel signal is prohibited.

[0032] It might occur that the unmodified conversion, such as by meansof the device of FIG. 1, of combinations of two subsequent 2-bit sourcewords might violate the d=1 constraint. Those combinations are thecombinations; ‘01 01’, which by unmodified conversion would lead to thetwo 3-bit channel words ‘101 101’; ‘01 00’, which by unmodifiedconversion would lead to the two 3-bit channel words ‘101 100’; ‘11 01’,which by unmodified conversion would lead to the two 3-bit channel words‘001 101’ and ‘11 00’, which by unmodified conversion would lead to thetwo 3-bit channel words ‘001 100’.

[0033] The occurrence of such combinations should be detected so that amodified encoding of blocks of two 2-bit source words into blocks of two3-bit channel words can take place. A modified embodiment of a device ofFIG. 1 which is, in addition to the ‘normal’ encoding of 2-bit sourcewords into 3-bit channel words, capable of detecting the aboveidentified combinations, and is capable of realizing a modifiedencoding, such that the d=1 constraint in the channel signal is stillsatisfied, is shown in FIG. 2a.

[0034] The device of FIG. 2a includes a shift register having four cellsX₁ to X₄ so as to receive four consecutive bits (x₁,x₂,x₃,x₄) of theserial bitstream of the source signal S. Outputs of the four cells arecoupled to corresponding inputs i₁ to i₄ respectively of the logiccircuit LC′. The device further comprises detector unit D1. The detectorunit D1 is adapted to detect the position in the serial bitstream of thesource signal where unmodified encoding of single source words in thebitstream into corresponding single channel words would lead to aviolation of the d=1 constraint in the channel signal C, and are adaptedto supply a control signal at its output 10 in response to suchdetection.

[0035] The output 10 of the detector unit D1 is coupled to a controlsignal input 12 of the logic circuit LC′. The logic circuit LC′ has sixoutputs o₁ to o₆, which are coupled to inputs of cells Y₁ to Y₆respectively of second shift register 4′.

[0036] In the absence of a control signal at the control signal input12, the logic circuit LC′ converts the first 2-bit source word ‘x₁ x₂’into the three bit channel word ‘y₁ y₂ y₃’ in conformity with table Igiven above. As soon as the detector circuit D1 detects a combination oftwo 2-bit source words (x₁x₂,x₃,x₄) which equals one of the combinationsgiven above, the logic circuit LC′ converts the combination inaccordance with the modified coding as given in the following table:TABLE II source words unmodified coding modified coding 01 01 101 101100 010 01 00 101 100 101 010 11 01 001 101 000 010 11 00 001 100 001010

[0037] As can be seen from the table, unmodified conversion of thesingle two 2-bit source words leads to a violation of the d=1constraint, as two ‘ones’ occur at the boundary between the two channelwords obtained. The logic circuit LC′ is therefore adapted to convert ina modified coding mode, the blocks of two 2-bit source words given inthe left column of the above table into the blocks of two 3-bit channelwords as given in the right column in the above table II. As can beseen, no violation of the d=1 constraint occurs anymore. Moreover, themodified encoding in the same way is parity preserving. This is correct,for the reason that twice a parity inverting conversion of a 2-bitsource word into a 3-bit channel word, leads to a parity preservationfor the combined conversion.

[0038] This means in the present situation that, if the number of ‘ones’in the blocks of two 2-bit source words is odd (even), the number of‘ones’ in the block of two 3-bit channel words obtained is odd (even).Further, one of the two 2-bit source words, which is in the above tablethe second one, is encoded into a 3-bit channel word which is unequal toone of the four channel words of table I. The reason for this is that onthe receiver side, a detection of this 3-bit channel word not belongingto the set of four 3-bit channel words of the table I is possible, sothat a corresponding decoding, which is the inverse of the encoding asdefined with reference to table II, can be realized.

[0039] The block of two 3-bit channel words obtained by means of theencoding in conformity with table II, is supplied by the logic circuitLC′ to its outputs o₁ to o₆, which channel words are supplied to the sixcells Y₁, to Y₆ of the shift register 4′. It is clear from theembodiment described that the situations where a modified encoding isneeded is detected by means of the detector D1 using the source words.

[0040] A different construction of the device for carrying out themodified encoding described with reference to the table II is shown inFIG. 2b. In this case, detection of the situations where a modifiedcoding should be carried out is decided using the converted channelwords. The device of FIG. 2b includes a detector D1′ having 6 inputs forreceiving two subsequent 3-bit channel words obtained by means of theunmodified encoding. The detector D1′ detects whether the two subsequent3-bit channel words obtained using the unmodified coding equal one ofthe four 6-bit sequences given in the middle column under ‘unmodifiedcoding’ of table II. If so, the detector D1′ issues a switching signalat its output 10 and an address signal AD at its output 10′. Theswitching signal is applied to a switching signal input 45 of the shiftregister 4″. The address signal AD is applied to an address signal input46 of a ROM 47. The detector D1′ generates one of four possible addresssignals AD1 to AD4, in response to the detection of a corresponding oneof the four 6-bit sequences in the middle column of table II. As anexample, the address signal AD1 is generated when the detector D1′detects the sequence ‘101101’ and generates the address signal AD4 upondetection of the 6-bit sequence ‘001100’. The ROM 47 has the 6-bitsequences shown in the right column of table II stored. Upon the receiptof the address signal AD1, the ROM supplies the 6-bit sequence ‘100 010’at its outputs o₁ to o₆, and upon the receipt of the address signal AD2,the ROM supplies the 6-bit sequence ‘101 010’ at its outputs. Upon thereceipt of the address signal AD3, the ROM supplies the 6-bit sequence‘000 010’ at its outputs, and upon the receipt of the address signalAD4, the ROM supplies the 6-bit sequence ‘001 010’ at its outputs. Eachmemory location of the shift register 4″ has now two inputs, one of thembeing coupled with a corresponding output of the logic circuit LC′, theother being coupled to a corresponding output of the ROM 47.

[0041] In the normal situation, when the d=1 constraint is not violated,unmodified conversion is carried out, and the switching signal is absentso that the shift register accepts the bits supplied by the logiccircuit LC′ via the upper inputs of the shift register 4″. If the d=1constraint is violated, the switching signal applied to the switchingsignal input 45 results in the shift register to accept the 6-bitsequence, which is the modified sequence, applied by the ROM to thelower inputs of the shift register 4″.

[0042] The k-constraint in a (d,k) sequence means that a concatenationof at most k ‘zeroes’ between two subsequent ‘ones’ in the channelsignal are allowed.

[0043] It might occur that the unmodified conversion of three subsequent2-bit source words might violate the k-constraint.

[0044] As an example: the sequence of source words ‘10 10 10’ would byunmodified conversion lead to the three 3-bit channel words ‘000 000000’. If a (d,k) sequence should be obtained where k equals 6, 7 or 8,such combination of three 3-bit channel words should not occur.

[0045] Another example is the sequence of source words ‘10 10 11’ whichby unmodified conversion would lead to the three 3-bit channel words‘000 000 001’. This combination of three 3-bit channel words does notsatisfy a k=6 or k=7 constraint. Moreover, this combination of three3-bit channel words can follow a previous channel word that ends with a‘0’, so that it might lead to a violation of a k=8 constraint. Further,the combination ends with a ‘1’, so that it might lead to a violation ofthe d=1 constraint, if the combination is followed by a 3-bit channelword that starts with a ‘1’. An equivalent reasoning is valid for thesequence of source words ‘00 10 10’.

[0046] A further example is the sequence of source words ‘00 10 11’which by unmodified conversion would lead to the three 3-bit channelwords ‘100 000 001’. This combination can, in the same way as givenabove, lead to a violation of the d=1 constraint.

[0047] The occurrence of such combinations should be detected so that amodified encoding can take place. An embodiment of a device which is, inaddition to the ‘normal’ encoding of 2-bit source words into 3-bitchannel words, capable of detecting the above identified combinations,and is capable of realizing a modified encoding, is shown in FIG. 3.

[0048] The device of FIG. 3 includes a shift register 2″ having sixcells X₁ to X₆ so as to receive six consecutive bits of the serialbitstream of the source signal S. Outputs of the six cells are coupledto corresponding inputs i₁ to i₆ respectively of the logic circuit LC″.The device further comprises detector means D2. The detector means D2are adapted to detect the position in the serial bitstream of the sourcesignal where unmodified encoding of the bitstream would lead to aviolation of the k-constraint in the channel signal C, and are adaptedto supply a control signal at its output 15 in response to suchdetection.

[0049] The outputs of the six cells are also coupled to four inputs i₁to i₆ respectively of logic circuit LC″. The output 15 of the detectormeans D2 is coupled to a control signal input 16 of the logic circuitLC″. The logic circuit LC″ has nine outputs o₁ to o₉, which are coupledto inputs of cells Y₁ to Y₉ respectively of second shift register 4″.

[0050] In the absence of a control signals at the control signal inputs12 and 16, the logic circuit LC′ converts a single 2-bit source word ‘x₁x₂’ into a single 3-bit channel word ‘y₁ y₂ y₃’ in conformity with tableI given above. As soon as the detector circuit D1 detects a block of two2-bit source words ‘x₁ x₂, x₃ x₄’ which equals one of the combinationsgiven in table II above, the logic circuit LC″ converts the combinationin accordance with the conversion rule as given in table II, so as toobtain a block of two 3-bit channel words ‘y₁ y₂ y₃ y₄ y₅ y₆’.

[0051] As soon as the detector D2 detects a block of three 2-bit sourcewords ‘x₁ x₂ x₃ x₄, x₅ x₆’ which equals one of the combinations givenabove, the logic circuit LC″ converts the block in accordance with themodified coding as given in the following table, so as to obtain a blockof three 3-bit channel words: TABLE III source words unmodified codingmodified coding 10 10 10 000 000 000 000 010 010 10 10 11 000 000 001001 010 010 00 10 11 100 000 001 101 010 010 00 10 10 100 000 000 100010 010

[0052] The logic circuit LC∝ is adapted to convert in a modified codingmode, the blocks of three 2-bit source words given in the left column ofthe above table III into the blocks of three 3-bit channel words asgiven in the right column in the above table. By realizing the modifiedencoding as per table III, a channel signal has been obtained whichsatisfies the k=8 constraint. Moreover, the modified encoding in thesame way is parity inverting. This means in the present situation that,if the number of ‘ones’ in the combination of three 2-bit source wordsis odd (even), the number of ‘ones’ in the combination of the three3-bit channel words obtained is even (odd). Further, two of the three2-bit source words, which is in the above table the second one and thethird one, is encoded into a 3-bit channel word which is unequal to oneof the four channel words of table I. The reason for this is that on thereceiver side, a detection of these two consecutive 3-bit channel wordsnot belonging to the set of four 3-bit channel words of the table I ispossible, so that a corresponding decoding, which is the inverse of theencoding as defined with reference to table III, can be realized.

[0053] The combination of three 3-bit channel words obtained by means ofthe encoding in conformity with table III, is supplied by the logiccircuit LC″ to its outputs o₁ to o₉, which channel words are supplied tothe nine cells Y₁ to Y₉ of the shift register 4″. The serial datastreamof the channel signal C is supplied to the output terminal 8.

[0054] It will be evident that, in the same way as described withreference to FIG. 2b, the detection of the violation of the k-constraintcan be done on the channel signal level, instead of the source signallevel.

[0055] It has been said previously that other conversion rules forconverting single 2-bit source words into single 3-bit channel words arepossible. Those conversion rules are given in the following threetables. TABLE IV source word channel word (x₁,x₂) (y₁,y₂,y₃) SW₁ 01 CW₁101 SW₂ 00 CW₂ 001 SW₃ 11 CW₃ 100 SW₄ 10 CW₄ 000

[0056] TABLE V source word channel word (x₁,x₂) (y₁,y₂,y₃) SW₁ 01 CW₁000 SW₂ 00 CW₂ 100 SW₃ 11 CW₃ 001 SW₄ 10 CW₄ 101

[0057] TABLE VI source word channel word (x₁,x₂) (y₁,y₂,y₃) SW₁ 01 CW₁000 SW₂ 00 CW₂ 001 SW₃ 11 CW₃ 100 SW₄ 10 CW₄ 101

[0058] It is evident that extensions of those conversion rules forencoding blocks of two or three 2-bit source words into blocks of two orthree 3-bit channel words can be obtained using the teachings givenabove.

[0059] A further embodiment of an encoder is explained with reference tothe following table VII. This table shows the conversion rule for anencoder capable of encoding 3-bit source words into 4-bit channel words.TABLE VII source word channel word (x₁,x₂,x₃) (y₁,y₂,y₃,y₄) SW₁ 001 CW₁0000 SW₂ 000 CW₂ 0001 SW₃ 011 CW₃ 0100 SW₄ 010 CW₄ 0101 SW₅ 101 CW₅ 1000SW₆ 100 CW₆ 1001 SW₇ 111 CW₇ 1010 SW₈ 110 CW₈ 0010

[0060] As has been said previously, the devices described above are verysuitable in combination with a converter unit in which one bit isinserted after each q bits in a serial datastream in order to realize apolarity conversion, or not. FIG. 4 shows such combination, where theconverter unit 40 is followed by the device 7′ in accordance with thepresent invention 41, which device 7′ is subsequently followed by a 1T-precoder 42, well known in the art. The output signal of the 1T-precoder 42 is applied to a control signal generator 43, whichgenerates the control signal for the converter unit 40, so as to controlwhether a ‘0’ or a ‘1’ is inserted in the serial datastream applied tothe device 7′. Inserting a ‘0’ or a ‘1’ bit always leads to either anincrease and decrease, respectively, or vice versa, in the runningdigital sum value at the output of the precoder 42.

[0061] By means of the arrangement shown in FIG. 4 it is possible toembed a tracking tone of a certain frequency in the serial datastream,or keep the DC content of the datastream to zero. Further, when thedevice 7′ is adapted to generate a (d,k) sequence as explained above, itcauses the output signal of the arrangement of FIG. 4 to be a (d,k) RLLoutput signal. Embodiments of the converter 40 are given in Bell SystemTechnical Journal, Vol 53, No. 6, pp. 1103-1106.

[0062]FIG. 5 shows a decoding device for decoding the serial datastreamobtained by the encoding device of FIG. 3 so as to obtain a binarysource signal. The decoding device has an input terminal 50 forreceiving the channel signal, which input terminal 50 is coupled to aninput 56 of a shift register 51, comprising nine cells Y₁ to Y₉. Theshift register 51 functions as a serial-parallel converter so thatblocks of three 3-bit channel words are applied to inputs i₁ to i₉ of alogic circuit 52. The logic circuit 52 comprises the three tables I, IIand III. Outputs o₁ to o₆ of the logic circuit 52 are coupled to inputsof cells X₁ to X₆ of a shift register 54, which has an output 57 coupledto an output terminal 55. A detector circuit 53 is present having inputsi₁ to i₆ coupled to outputs of cells Y₄ to Y₉ respectively of the shiftregister 51, and outputs o₁ and o₂ coupled to control inputs c₁ and c₂respectively of the logic circuit 52. The detector circuit 53 is capableof detecting a ‘010’ bit pattern in the cells Y₄, Y₅ and Y₆ of the shiftregister 51 and is capable of detecting a bit pattern ‘010010’ in thecells Y₄ to Y₉ of the shift register 51.

[0063] Upon detection of the ‘010010’ bitpattern, the detector circuit53 generates a control signal on its output o₂, and upon detection of a‘010’ bit pattern in the cells Y₄, Y₅ and Y₆, whilst there is no ‘010’bit pattern in the cells Y₇, Y₈ and Y₉, it generates a control signal onits output o₁.

[0064] In the absence of the control signals, the logic circuit 52converts the 3-bit channel word stored in the cells Y₁, Y₂ and Y₃ intoits corresponding 2-bit source word, as per the conversion table I, andsupplies the 2-bit source word to the cells X₁ and X₂. In the presenceof the control signal at the input c₁, the logic circuit 52 converts theblock of two 3-bit channel words stored in the cells Y₁ to Y₆ into ablock of two 2-bit source words, as per the conversion table II, andsupplies the two 2-bit source words to the cells X₁ to X₄. In thepresence of the control signal at the input c₂, the logic circuit 52converts the block of three 3-bit channel words stored in the cells Y₁to Y₉ into a block of three 2-bit source words, as per the conversiontable III, and supplies the three 2-bit source words to the cells X₁ toX₆. In this way, the serial datastream of the channel signal isconverted into the serial datastream of the source signal.

[0065] The encoded information supplied to the input 50 could have beenobtained from reproducing the information from a record carrier, such asa magnetic record carrier 23 or an optical record carrier 23′. Thedevice of FIG. 5 thereto comprises a read unit 62 form reading theinformation from a track on the record carrier, where the unit 62comprises a read head 64 for reading the information from said track.

[0066] Next, another parity inverting 2-to-3 bit conversion code will bedescribed, resulting in a (1,7) sequence. The main conversion table isas follows: source word Channel word SW₁ 01 CW₁ x0x SW₂ 00 CW₂ 001 SW₃11 CW₃ 010

[0067] In this table, conversion of the source word ‘01’ is dependent ofthe last bit of the channel word obtained from converting the directlypreceding 2-bit source word. When this last bit is a ‘0’ bit, theconversion results into the 3-bit word ‘101’ and when this last bit is a‘1’ bit, the conversion results into the 3-bit word ‘000’.

[0068] A first substitution table is present for converting specificblocks of two 2-bit source words. This first substitution table is asfollows: block of 2 source words block of 2 channel words 10 01 010 10010 00 010 000 10 11 000 100

[0069] A second substitution table is present for converting specificblocks of three 2-bit source words. This second substitution table is asfollows: block of 3 source words block of 3 channel words 10 10 01 000100 100 10 10 00 001 100 000 10 10 11 010 100 100 10 10 10 010 100 000

[0070] A third substitution table is present for converting specificblocks of four 2-bit source words. This third substitution table is asfollows: block of 4 source words block of 4 channel words 10 10 00 10000 100 100 100 10 10 10 10 010 100 100 100

[0071] Further, unmodified conversion of the following sequence 01 11 01xy could lead to the following channel sequence: 101 010 101 010, wherethe conversion of the first 2-bit source word apparently led to the3-bit channel word ‘101 ’ and xy is a 2-bit source word leading to the3-bit channel word ‘010’. Such sequence is unwanted, as it violates arequirement for the length of a repeated minimum transition runlength(RMTR). Therefore, upon occurrence of such sequence, this sequence isconverted into the sequence 001 000 000 010.

[0072] Whilst the invention has been described with reference topreferred embodiments thereof, it is to be understood that these are notlimitative examples. Thus, various modifications may become apparent tothose skilled in the art, without departing from the scope of theinvention, as defined by the claims. As an example, the decoding deviceof FIG. 5 could be modified into a device in which the detector 53detects the various modified decoding situations from the decodedinformation, instead from the encoded information, as disclosed in FIG.5. It should further be noted that, as an example, the converter unit 7″and the precoder 42 could have been into one combined unit, where,dependent of incoming n-bit source words, via a conversion table, thosen-bit source words are directly converted into 3-bit output words of thecombined unit. Further, it should be noted that the parity invertingconversion as claimed could have been obtained by applying a paritypreserving coder, such as described in U.S. Pat. No. 5,477,222, andEXORing the 2-bit source words with either ‘10’ or ‘01’ (EXORing, in thesense of: msb of the 2-bit source word with the msb of ‘10’ or ‘01’, and1sb of the 2-bit source word with the 1sb of ‘10’ or ‘01’), prior toapplying the 2-bit source words to the parity preserving coder.

[0073] Further, any reference signs do not limit the scope of theclaims. The invention can be implemented by means of both hardware andsoftware, and several “means” may be represented by the same item ofhardware. The word ‘comprising’ does not exclude the presence of otherelements or steps than those listed in a claim. Also, the word “a” or 37an” preceding an element does not exclude the presence of a plurality ofsuch elements. In addition, the invention lies in each and every novelfeature or combination of features.

1. A device for encoding a stream of databits of a binary source signalinto a stream of databits of a binary channel signal, wherein thebitstream of the source signal is divided into n-bit source words, whichdevice comprises converting means adapted to convert said source wordsinto corresponding m-bit channel words, characterized in that, theconverting means are adapted to convert a block of p consecutive n-bitsource words into a corresponding block of p consecutive m-bit channelwords, such that the conversion for each block of p consecutive n-bitsource words is parity inverting, where n, m and p are integers, m>n≧1,p≧1, and where p is an odd integer and can vary.
 2. A device as claimedin claim 1, characterized in that, m=n+1.
 3. A device as claimed inclaim 2, characterized in that, n=2.
 4. Device as claimed in claim 3,characterized in that, the device is adapted to convert single sourcewords into corresponding single channel words in accordance with thefollowing table: source word Channel word SW₁ 00 CW₁ 100 SW₂ 01 CW₂ 101SW₃ 10 CW₃ 000 SW₄ 11 CW₄ 001


5. A device as claimed in claim 3 or 4, wherein the converting means areadapted to convert 2-bit source words into corresponding 3-bit channelwords, so as to obtain a channel signal in the form of a (d,k) sequence,where d=1, the device further comprising means for detecting theposition in the bitstream of the source signal where encoding of single2-bit source words into corresponding single channel words would lead toa violation of the d-constraint at the channel word boundaries and forsupplying a control signal in response to said detection, characterizedin that, in the absence of the control signal, the converting means areadapted to convert single 2-bit source words into corresponding single3-bit channel words, such that the conversion for each 2-bit source wordis parity inverting.
 6. Device as claimed in claim 5, wherein, in thepresence of the control signal, occurring during the conversion of twoconsecutive source words, the converting means are adapted to convert ablock of said two consecutive 2-bit source words into a block of twocorresponding 3-bit channel words, such that one of the two source wordsin the block of source words is converted into a 3-bit channel wordwhich is not identical to one of the four channel words CW₁ to CW₄, inorder to preserve the d=1 constraint, characterized in that, in thepresence of said control signal, the converting means are furtheradapted to convert the block of said two subsequent 2-bit source wordsinto a corresponding block of two subsequent 3-bit channel words, suchthat the conversion for said block of two subsequent 2-bit source wordsis parity preserving.
 7. Device as claimed in claim 1 or 6,characterized in that, the converting means are adapted to convertblocks of two consecutive 2-bit source words into blocks of twoconsecutive 3-bit channel words in accordance with the coding given inthe following table: block of 2 source words block of 2 channel words 0101 100 010 01 00 101 010 11 01 000 010 11 00 001 010


8. Device as claimed in claim 1, 6 or 7, where k has a value larger than5, the device being further provided with means for detecting theposition in the bitstream of the source signal where encoding of single2-bit source words into single 3-bit channel words would lead to aviolation of the k-constraint and for supplying a second control signalin response to said detection, characterized in that, in the presence ofthe second control signal, occurring during the conversion of threeconsecutive 2-bit source words, the converting means are adapted toconvert a block of said three consecutive 2-bit source words into ablock of corresponding three consecutive 3-bit channel words, such thatthe conversion for said block of three 2-bit source words is parityinverting, the converting means are further adapted to convert two ofthe three source words in the block into corresponding 3-bit channelwords not identical to the four channel words CW₁ to CW₄, in order topreserve the k constraint.
 9. Device as claimed in claim 1 or 8,characterized in that, the converting means are adapted to convertblocks of three consecutive 2-bit source words into blocks of threeconsecutive 3-bit channel words in accordance with the coding given inthe following table: block of 3 source words block of 3 channel words 1010 10 000 010 010 10 10 11 001 010 010 00 10 11 101 010 010 00 10 10 100010 010


10. Device as claimed in anyone of the preceding claims, characterizedin that the conversion means are adapted to carry out a signalprocessing on the binary source signal equivalent to the conversion ofthe blocks of p consecutive source words into the blocks of pconsecutive channel words, followed by an aT precoding of said channelwords.
 11. Device as claimed in claim 1 or 10, characterized in that itfurther comprises bitadding means for adding one bit to subsequentblocks of q bits of the source signal.
 12. Device as claimed in anyoneof the preceding claims, characterized in that it further comprisesmeans for recording the stream of databits of the binary channel signalin a track on the record carrier.
 13. Method of encoding a stream ofdatabits of a binary source signal into a stream of databits of a binarychannel signal, wherein the bitstream of the source signal is dividedinto n-bit source words, the method comprising the step of convertingsaid source words into corresponding m-bit channel words, characterizedin that, the converting step comprises the conversion of a block of pconsecutive n-bit source words into a corresponding block of pconsecutive m-bit channel words, such that the conversion for each blockof p consecutive n-bit source words is parity inverting, where n, m andp are integers, m>n≧1, p≧1, and where p can vary.
 14. Device fordecoding a stream of data bits of a binary channel signal into a streamof databits of a binary source signal, wherein the bitstream of thechannel signal is divided into m-bit channel words, which devicecomprises deconverting means adapted to deconvert m-bit channel wordsinto corresponding n-bit source words, characterized in that, thedeconverting means are adapted to deconvert a block of p consecutivem-bit channel words into a corresponding block of p consecutive n-bitsource words, such that the conversion for each block of p consecutivem-bit channel words is parity inverting, where n, m and p are integers,m>n, p≧1, and where p is an odd integer and can vary.